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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 document no. m15867ej5v0ds00 (5th edition) date published august 2002 ns cp (k) printed in japan mos integrated circuit pd4664312-x 64m-bit cmos mobile specified ram 4m-word by 16-bit extended temperature operation preliminary data sheet the mark ? ? ? ? shows major revised points. description the pd4664312-x is a high speed, low power, 67,108,864 bits (4,194,304 words by 16 bits) cmos mobile specified ram featuring low power static ram compatible function and pin configuration. the pd4664312-x is fabricated with advanced cmos technology using one-transistor memory cell. the pd4664312-x is packed in 93-pin tape fbga. features ? 4,194,304 words by 16 bits organization ? fast access time: 65, 75 ns (max.) ? fast page access time: 18, 25 ns (max.) ? byte data control: /lb (i/o0 to i/o7), /ub (i/o8 to i/o15) ? low voltage operation: 2.7 to 3.1 v (-b65x) 2.7 to 3.1 v (chip), 1.65 to 2.1 v (i/o) (-be75x) ? operating ambient temperature: t a = ?25 to +85 c ? output enable input for easy application ? chip enable input: /cs pin ? standby mode input: mode pin ? standby mode1: normal standby (memory cell data hold valid) ? standby mode2: density of memory cell data hold is variable pd4664312 access operating supply operating supply current time voltage ambient at operating at standby a (max.) ns (max.) v temperature ma (max.) density of data hold chip i/o c 64m bits 16m bits 8m bits 4m bits 0m bit -b65x 65 2.7 to 3.1 ? ?25 to +85 45 100 60 50 45 10 -be75x note 75 2.7 to 3.1 1.65 to 2.1 40 note under development
preliminary data sheet m15867ej5v0ds 2 pd4664312-x ordering information part number package access time operating supply voltage operating ns (max.) v temperature chip i/o c pd4664312f9-b65x-cr2 93-pin tape fbga (12 x 9) 65 2.7 to 3.1 ? ?25 to +85 pd4664312f9-be75x-cr2 note 75 2.7 to 3.1 1.65 to 2.1 note under development
preliminary data sheet m15867ej5v0ds 3 pd4664312-x pin configurations /xxx indicates active low si gnal. 93-pin tape fbga (12 x 9) [ pd4664312f9-b65x-cr2 ] top view gnd i/o9 i/o5 a7 /oe i/o7 i/o4 i/o0 a6 a18 a11 a8 a5 i/o8 i/o12 a13 a17 nc nc i/o10 nc /we v cc a16 i/o11 nc nc a12 i/o6 i/o13 a9 a15 a19 i/o14 /cs i/o15 i/o1 a1 a2 a4 a10 nc i/o2 a0 a3 mode a20 a14 /lb nc nc /ub i/o3 a21 nc gnd abcdefgh nc nc nc nc nc nc nc nc nc nc nc nc nc m kl j 10 9 8 7 6 5 4 3 2 1 nc nc nc nc nc nc nc nc nc nc nc nc lkjhgfedcba m bcde fghj klm 10 9 8 7 6 5 4 3 2 1 a top view bottom view n p n p nc nc nc nc n p nc nc nc nc nc nc nc nc note some signals can be applied because this pin is not internally connected. remarks refer to package drawing for the index mark. a0 to a21 : address inputs i/o0 to i/o15 : data inputs / outputs /cs : chip select mode : standby mode /we : write enable /oe : output enable /lb, /ub : byte data select v cc : power supply gnd : ground nc note : no connection
preliminary data sheet m15867ej5v0ds 4 pd4664312-x 93-pin tape fbga (12 x 9) [ pd4664312f9-be75x-cr2 ] top view gnd i/o9 i/o5 a7 /oe i/o7 i/o4 i/o0 a6 a18 a11 a8 a5 i/o8 i/o12 a13 a17 nc nc i/o10 nc /we v cc a16 i/o11 nc nc a12 i/o6 i/o13 a9 a15 a19 i/o14 /cs i/o15 i/o1 a1 a2 a4 a10 v cc q i/o2 a0 a3 mode a20 a14 /lb nc nc /ub i/o3 a21 nc gnd abcdefgh nc nc nc nc nc nc nc nc nc nc nc nc nc m kl j 10 9 8 7 6 5 4 3 2 1 nc nc nc nc nc nc nc nc nc nc nc nc lkjhgfedcba m bcde fghj klm 10 9 8 7 6 5 4 3 2 1 a top view bottom view n p n p nc nc nc nc n p nc nc nc nc nc nc nc nc note some signals can be applied because this pin is not internally connected. remarks refer to package drawing for the index mark. a0 to a21 : address inputs i/o0 to i/o15 : data inputs / outputs /cs : chip select mode : standby mode /we : write enable /oe : output enable /lb, /ub : byte data select v cc : power supply v cc q : input / output power supply gnd : ground nc note : no connection
preliminary data sheet m15867ej5v0ds 5 pd4664312-x block diagram a0 a21 i/o8 to i/o15 /we /oe /ub /lb i/o0 to i/o7 v cc v cc q gnd mode refresh counter refresh control standby mode control address buffer address buffer row decoder memory cell array 67,108,864 bits input data controller sense amplifier / switching circuit column decoder output data controller /cs remark v cc q is the input / output power supply for -be75x.
preliminary data sheet m15867ej5v0ds 6 pd4664312-x truth table /cs mode /oe /we /lb /ub mode i/o supply i/o0 to i/o7 i/o8 to i/o15 current hh not selected (standby mode 1) high-z high-z i sb1 h h h not selected (standby mode 1) high-z high-z l not selected (standby mode 2) note high-z high-z i sb2 lhhh output disable high-z high-z i cca l h l l word read d out d out l h lower byte read d out high-z h l upper byte read high-z d out hlll word write d in d in l h lower byte write d in high-z h l upper byte write high-z d in note mode pin must be fixed to high level except standby mode 2. (refer to 2.3 standby mode status transition ). remark : v ih or v il , h: v ih , l: v il
preliminary data sheet m15867ej5v0ds 7 pd4664312-x contents 1. initialization ............................................................................................................. ....................................................... 8 2. partial refresh ............................................................................................................ ................................................... 9 2.1 standby mode.............................................................................................................. ............................................. 9 2.2 density switching......................................................................................................... ............................................. 9 2.3 standby mode status transition............................................................................................ ................................... 9 2.4 addresses for which partial refresh is supported .......................................................................... ...................... 10 3. page read operation ........................................................................................................ .......................................... 11 3.1 features of page read operation ........................................................................................... ............................... 11 3.2 page length ............................................................................................................... ............................................ 11 3.3 page-corresponding addresses.............................................................................................. ............................... 11 3.4 page start address........................................................................................................ ......................................... 11 3.5 page direction ............................................................................................................ ............................................ 11 3.6 interrupt during page read operation...................................................................................... .............................. 11 3.7 when page read is not used................................................................................................ ................................... 11 4. mode register settings..................................................................................................... ........................................... 12 4.1 mode register setting method .............................................................................................. ................................. 12 4.2 cautions for setting mode register ........................................................................................ ................................ 13 5. electrical specifications .................................................................................................. ............................................. 14 6. timing charts.............................................................................................................. ................................................. 20 7. package drawing ............................................................................................................ ............................................. 30 8. recommended soldering conditions ........................................................................................... ............................... 31 9. revision history ........................................................................................................... ................................................ 32
preliminary data sheet m15867ej5v0ds 8 pd4664312-x 1. initialization initialize the pd4664312-x at power application using the following sequence to stabilize internal circuits. (1) following power application, make mode high level after fixing mode to low level for the period of t vhmh . make /cs high level before making mode high level. (2) /cs and mode are fixed to high level for the period of t mhcl . normal operation is possible after the completion of initialization. figure1-1. initialization timing chart /cs (input) v cc mode (input) t mhcl initialization t chmh t vhmh v cc (min.) normal operation cautions 1. make mode low level when starting the power supply. 2. t vhmh is specified from when the power supply voltage reaches the prescribed minimum value (v cc (min.)).
preliminary data sheet m15867ej5v0ds 9 pd4664312-x 2. partial refresh 2.1 standby mode in addition to the regular standby mode (standby mode 1) with a 64m bits density, standby mode 2, which performs partial refresh, is also provided. 2.2 density switching in standby mode 2, the densities that can be selected for performing refresh are 16m bits, 8m bits, 4m bits, and 0m bit. the density for performing refresh can be set with the mode register. once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. however, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. (for how to perform mode register settings, refer to section 4. mode register settings .) 2.3 standby mode status transition in standby mode 1, mode and /cs are high level, or mode, /lb and /ub are high level. in standby mode 2, mode is low level. in standby mode 2, if 0m bit is set as the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal operation from standby mode 2. when the density has been set to 16m bits, 8m bits, or 4m bits in standby mode 2, it is not necessary to perform initialization to return to normal operation from standby mode 2. for the timing charts, refer to figure 6-14. standby mode 2 (data hold: 16m bits / 8m bits / 4m bits) entry / exit timing chart , figure 6-15. standby mode 2 (data not held) entry / exit timing chart .
preliminary data sheet m15867ej5v0ds 10 pd4664312-x figure 2-1. standby mode state machine power on active mode = v ih mode = v il mode = v il /cs = v il , mode = v ih standby mode 1 standby mode 2 (16m bits / 8m bits / 4m bits) /cs = v il initial state initialization standby mode 2 (data not held) /cs = v il , mode = v ih mode = v il mode = v il mode = v ih , /cs = v ih or /lb, /ub = v ih 2.4 addresses for which partial refresh is supported data hold density correspondence address 16m bits 000000h to 0fffffh 8m bits 000000h to 07ffffh 4m bits 000000h to 03ffffh
preliminary data sheet m15867ej5v0ds 11 pd4664312-x 3. page read operation 3.1 features of page read operation features 8 words mode page length 8 words page read-corresponding addresses a2, a1, a0 page read start address don?t care page direction don?t care interrupt during page read operation enabled note note an interrupt is output when /cs = h or in case a3 or a higher address changes. 3.2 page length 8 words is supported as the page lengths. 3.3 page-corresponding addresses the page read-enabled addresses are a2, a1, and a0. fix addresses other than a2, a1, and a0 during page read operation. 3.4 page start address since random page read is supported, any address (a2, a1, a0) can be used as the page read start address. 3.5 page direction since random page read is possible, there is not restriction on the page direction. 3.6 interrupt during page read operation when generating an interrupt during page read, either make /cs high level or change a3 and higher addresses. 3.7 when page read is not used since random page read is supported, even when not using page read, random access is possible as usual.
preliminary data sheet m15867ej5v0ds 12 pd4664312-x 4. mode register settings the partial refresh density can be set using the mode register. since the initial value of the mode register at power application is undefined, be sure to set the mode register after initialization at power application. when setting the density of partial refresh, data before entering the partial refresh mode is not guaranteed. (this is the same for re- setup.) however, since partial refresh mode is not entered unless mode = l when partial refresh is not used, it is not necessary to set the mode register. moreover, when using page read without using partial refresh, it is not necessary to set the mode register. 4.1 mode register setting method the mode register setting mode can be entered by successively writing two specific data after two continuous reads of the highest address (3fffffh). the mode register setting is a continuous four-cycle operation (two read cycles and two write cycles). commands are written to the command register. the command register is used to latch the addresses and data required for executing commands, and it does not have an exclusive memory area. for the timing chart and flow chart, refer to figure 6-12. mode register setting timing chart , figure 6-13. mode register setting flow chart . table 4-1. shows the commands and command sequences. table 4-1. command sequence command sequence 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle (read cycle) (read cycle) (write cycle) (write cycle) partial refresh density address data address data address data address data 16m bits 3fffffh ? 3fffffh ? 3fffffh 00h 3fffffh 04h 8m bits 3fffffh ? 3fffffh ? 3fffffh 00h 3fffffh 05h 4m bits 3fffffh ? 3fffffh ? 3fffffh 00h 3fffffh 06h 0m bit 3fffffh ? 3fffffh ? 3fffffh 00h 3fffffh 07h 4th bus cycle (write cycle) i/o 1514131211109876543210 mode register setting 0000000000000pl pd page length 1 8 words i/o1 i/o0 density partial refresh 0 0 16m bits density 0 1 8m bits 1 0 4m bits 1 1 0m bit
preliminary data sheet m15867ej5v0ds 13 pd4664312-x 4.2 cautions for setting mode register since, for the mode register setting, the internal counter status is judged by toggling /cs and /oe, toggle /cs at every cycle during entry (read cycle twice, write cycle twice), and toggle /oe like /cs at the first and second read cycles. if incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the mode register is not performed correctly. when the highest address (3fffffh) is read consecutively three or more times, the mode register setting entries are not performed correctly. (immediately after the highest address is read, the setting of the mode register is not performed correctly.) perform the setting of the mode register after power application or after accessing other than the highest address. once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. however, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. for the timing chart and flow chart, refer to figure 6-12. mode register setting timing chart , figure 6-13. mode register setting flow chart .
preliminary data sheet m15867ej5v0ds 14 pd4664312-x 5. electrical specifications absolute maximum ratings parameter symbol condition rating unit -b65x -be75x supply voltage v cc ?0.5 note to +4.0 ?0.5 note to +4.0 v input / output supply voltage v cc q ? ?0.5 note to +4.0 v input / output voltage v t ?0.5 note to v cc + 0.4 (4.0 v max.) ? 0.5 note to v cc q + 0.4 (4.0 v max. ) v operating ambient temperature t a ?25 to +85 ?25 to +85 c storage temperature t stg ?55 to +125 ?55 to +125 c note ?1.0 v (min.) (pulse width: 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition -b65x -be75x unit min. max. min. max. supply voltage v cc 2.7 3.1 2.7 3.1 v input / output supply voltage v cc q ? ? 1.65 2.1 v high level input voltage v ih 0.8v cc v cc +0.3 0.8v cc qv cc q+0.3 v low level input voltage v il ?0.3 note 0.2v cc ?0.3 note 0.2v cc qv operating ambient temperature t a ?25 +85 ?25 +85 c note ?0.5 v (min.) (pulse width: 30 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 8 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage, v i/o : input / output voltage 2. these parameters are not 100% tested.
preliminary data sheet m15867ej5v0ds 15 pd4664312-x dc characteristics (recommended operating conditions unless otherwise noted) (1/2) parameter symbol test condition density of -b65x unit data hold min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /cs = v ih or ?1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca /cs = v il , minimum cycle time, 45 ma i i/o = 0 ma standby supply current i sb1 /cs v cc ? 0.2 v, 64m bits 60 100 a mode v cc ? 0.2 v i sb2 /cs v cc ? 0.2 v, 16m bits 50 60 mode 0.2 v 8m bits 45 50 4m bits 40 45 0m bit 10 high level output voltage v oh i oh = ?0.5 ma 0.8v cc v low level output voltage v ol i ol = 1 ma 0.2v cc v remark v in : input voltage, v i/o : input / output voltage dc characteristics (recommended operating conditions unless otherwise noted) (2/2) parameter symbol test condition density of -be75x unit data hold min. typ. max. input leakage current i li v in = 0 v to v cc q ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc q, /cs = v ih or ?1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca /cs = v il , minimum cycle time, 40 ma i i/o = 0 ma standby supply current i sb1 /cs v cc ? 0.2 v, 64m bits 60 100 a mode v cc ? 0.2 v i sb2 /cs v cc ? 0.2 v, 16m bits 50 60 mode 0.2 v 8m bits 45 50 4m bits 40 45 0m bit 10 high level output voltage v oh i oh = ?0.5 ma 0.8v cc qv low level output voltage v ol i ol = 1 ma 0.2v cc qv remark v in : input voltage, v i/o : input / output voltage
preliminary data sheet m15867ej5v0ds 16 pd4664312-x ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions [ -b65x ] input waveform (rise and fall time 5 ns) test points 0.2vcc 0.8vcc vcc / 2 vcc / 2 vcc gnd 5ns output waveform test points vcc / 2 vcc / 2 [ -be75x ] input waveform (rise and fall time 5 ns) test points 0.2vccq 0.8vccq vccq / 2 vccq / 2 vccq gnd 5ns output waveform test points vccq / 2 vccq / 2 output load ac characteristics directed with the note should be measured with the output load shown in figure 5-1, figure 5-2 . figure 5-1. figure 5-2. [ -b65x ] [ -be75x ] c l : 30 pf c l : 30 pf 5 pf (t clz , t olz , t blz , t chz , t ohz , t bhz ) 5 pf (t clz , t olz , t blz , t chz , t ohz , t bhz ) i/o (output) 50 ? z o = 50 ? c l v cc / 2 i/o (output) 50 ? z o = 50 ? c l v cc q / 2
preliminary data sheet m15867ej5v0ds 17 pd4664312-x read cycle parameter symbol -b65x -be75x unit note min. max. min. max. read cycle time t rc 65 75 ns 1 address access time t aa 65 75 ns /cs access time t acs 65 75 ns /oe to output valid t oe 45 50 ns /lb, /ub to output valid t ba 65 75 ns output hold from address change t oh 55ns page read cycle time t prc 18 25 ns page access time t paa 18 25 ns /cs to output in low impedance t clz 10 10 ns 2 /oe to output in low impedance t olz 55ns /lb, /ub to output in low impedance t blz 55ns /cs to output in high impedance t chz 25 25 ns /oe to output in high impedance t ohz 25 25 ns /lb, /ub to output in high impedance t bhz 25 25 ns address set to /oe low level t aso 00ns /oe high level to address hold t ohah ?5 ?5 ns /cs high level to address hold t chah 00ns3 /lb, /ub high level to address hold t bhah 0 0 ns 3, 4 /cs low level to /oe low level t clol 0 10,000 0 10,000 ns 5 /oe low level to /cs high level t olch 45 45 ns /cs high level pulse width t cp 10 10 ns /lb, /ub high level pulse width t bp 10 10 ns /oe high level pulse width t op 2 10,000 2 10,000 ns 5 notes 1. output load: 30 pf 2. output load: 5 pf 3. when t aso | t chah |, | t bhah |, t chah and t bhah (min.) are ?15 ns. t chah , t bhah t aso /lb, /ub, /cs (input) address (input) /oe (input) 4. t bhah is specified from when both /lb and /ub become high level. 5. t clol and t op (max.) are applied while /cs is being hold at low level.
preliminary data sheet m15867ej5v0ds 18 pd4664312-x write cycle parameter symbol -b65x -be75x unit note min. max. min. max. write cycle time t wc 65 75 ns /cs to end of write t cw 55 60 ns address valid to end of write t aw 55 60 ns /lb, /ub to end of write t bw 55 60 ns write pulse width t wp 50 55 ns write recovery time t wr 00ns /cs pulse width t cp 10 10 ns /lb, /ub high level pulse width t bp 10 10 ns /we high level pulse width t whp 10 10 ns address setup time t as 00ns /oe high level to address hold t ohah ?5 ?5 ns /cs high level to address hold t chah 00ns1 /lb, /ub high level to address hold t bhah 0 0 ns 1, 2 data valid to end of write t dw 30 35 ns data hold time t dh 00ns /oe high level to /we set t oes 0 10,000 0 10,000 ns 3 /we high level to /oe set t oeh 10 10,000 10 10,000 ns notes 1. when t as | t chah |, | t bhah | and t cp 18 ns, t chah and t bhah (min.) are ?15 ns. t chah , t bhah t as /lb, /ub, /cs (input) address (input) /we (input) 2. t bhah is specified from when both /lb and /ub become high level. 3. t oes and t oeh (max.) are applied while /cs is being hold at low level.
preliminary data sheet m15867ej5v0ds 19 pd4664312-x initialization parameter symbol min. max. unit note power application to mode low level hold t vhmh 50 s /cs high level to mode high level t chmh 0ns following power application t mhcl 200 s mode high level hold to /cs low level standby mode 2 entry / exit parameter symbol min. max. unit note standby mode 2 entry t chml 0ns /cs high level to mode low level standby mode 2 exit to normal operation t mhcl1 30 ns 1 mode high level to /cs low level standby mode 2 exit to normal operation t mhcl2 200 s2 mode high level to /cs low level notes 1. this is the time it takes to return to normal operation from standby mode 2 (data hold: 16m bits / 8m bits / 4m bits). 2. this is the time it takes to return to normal operation from standby mode 2 (data not held).
preliminary data sheet m15867ej5v0ds 20 pd4664312-x 6. timing charts figure 6-1. read cycle timing chart 1 (/cs controlled) /cs (input) address (input) data out q2 i/o (output) high-z high-z high-z t rc /oe (input) data out q1 t rc t acs t acs t cp a1 a2 a3 t cp t clz t clz t chz t chz t chah t chah /lb, /ub (input) remark in read cycle, mode and /we should be fixed to high level. figure 6-2. read cycle timing chart 2 (/oe controlled) /cs (input) address (input) data out q2 i/o (output) high-z high-z high-z t rc /oe (input) t aso data out q1 t oe t rc t aa t aso t oe t aso t op t op a1 a2 a3 t ohz t olz t ohz t olz t ohah t ohah t aa /lb, /ub (input) t bhah t bhah remark in read cycle, mode and /we should be fixed to high level.
preliminary data sheet m15867ej5v0ds 21 pd4664312-x figure 6-3. read cycle timing chart 3 (/cs, /oe controlled) /cs (input) address (input) data out q2 i/o (output) high-z high-z high-z t rc /oe (input) data out q1 t rc t acs t aa a1 a2 a3 t clz t oe t ohz t chz t ohah t chah /lb, /ub (input) t clol t olz t ohz t ohah t aso t olz t oe t bhah t bhah remark in read cycle, mode and /we should be fixed to high level. figure 6-4. read cycle timing chart 4 (address controlled) /cs (input) address (input) data out q2 i/o (output) t rc /oe (input) data out q1 t aa a1 a2 a3 t rc t aa t oh t oh t oh /lb, /ub (input) remark in read cycle, mode and /we should be fixed to high level.
preliminary data sheet m15867ej5v0ds 22 pd4664312-x figure 6-5. read cycle timing chart 5 (/lb, /ub controlled) /cs (input) address (input) i/o (output) high-z high-z high-z t rc /oe (input) t rc a1 a2 a3 t bhah t bhah /lb, /ub (input) t ba t bhz data out q1 t blz t ba t bhz data out q2 t blz t bp t bp remark in read cycle, mode and /we should be fixed to high level. figure 6-6. page read cycle timing chart i/o (output) address (a3 to a21) (input) page address (a0 to a2) (input) /cs (input) /oe (input) t prc t prc t prc t rc t paa t oh t paa t oh t paa t oh t acs t oe t oh a n+1 a n+2 a n+3 a n+7 q n q n+1 q n+2 q n+3 q n+7 t chz t ohz a n t paa t oh t prc t paa t oh t prc t paa t oh t prc t paa t oh q n+4 q n+5 q n+6 a n+4 a n+5 a n+6 t prc high-z remarks 1. in read cycle, mode and /we should be fixed to high level. 2. /lb and /ub are low level.
preliminary data sheet m15867ej5v0ds 23 pd4664312-x figure 6-7. write cycle timing chart 1 (/cs controlled) t wc t as t wc t as t as a1 a2 a3 t cw t cw t wr t wr t cp t cp /cs (input) address (input) /we (input) /lb, /ub (input) data in d2 data in d1 t dw t dh t dw t dh /oe (input) t aso t ohah t oes t oeh i/o (input) high-z high-z high-z cautions 1. during address transition, at least one of pins /cs and /we, or both of /lb and /ub pins should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. in write cycle, mode and /oe should be fixed to high level. remark write operation is done during the overlap time of a low level /cs, /we, /lb and/or /ub.
preliminary data sheet m15867ej5v0ds 24 pd4664312-x figure 6-8. write cycle timing chart 2 (/we controlled) data in d2 t wc t as data in d1 t wc t as t whp a1 a2 a3 t cw t wr t cw t dw t dh t dw t dh t wp t wp /oe (input) t cp t aso t ohah t oes t oeh t bhah t bhah t wr t cp t chah t chah /cs (input) address (input) i/o (input) high-z high-z high-z /we (input) /lb, /ub (input) cautions 1. during address transition, at least one of pins /cs and /we, or both of /lb and /ub pins should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. in write cycle, mode and /oe should be fixed to high level. remark write operation is done during the overlap time of a low level /cs, /we, /lb and/or /ub.
preliminary data sheet m15867ej5v0ds 25 pd4664312-x figure 6-9. write cycle timing chart 3 (/we controlled) t wc t as t wc t as t aso a1 a2 a3 t wr t wr /oe (input) t ohah t oes t oeh t whp t aw t aw t dw t dh t dw t dh t wp t wp t bhah t bhah /cs (input) address (input) data in d2 i/o (input) high-z high-z high-z /we (input) data in d1 /lb, /ub (input) cautions 1. during address transition, at least one of pins /cs and /we, or both of /lb and /ub pins should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. in write cycle, mode and /oe should be fixed to high level. remark write operation is done during the overlap time of a low level /cs, /we, /lb and/or /ub.
preliminary data sheet m15867ej5v0ds 26 pd4664312-x figure 6-10. write cycle timing chart 4 (/lb, /ub controlled) t wc t as t wc t as a1 a2 a3 t wr t wr t dw t dh t dw t dh t bw t bw t bp t bp t aso /oe (input) t ohah t oes t oeh /cs (input) address (input) data in d2 i/o (input) high-z high-z high-z /we (input) data in d1 /lb, /ub (input) cautions 1. during address transition, at least one of pins /cs and /we, or both of /lb and /ub pins should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. in write cycle, mode and /oe should be fixed to high level. remark write operation is done during the overlap time of a low level /cs, /we, /lb and/or /ub.
preliminary data sheet m15867ej5v0ds 27 pd4664312-x figure 6-11. write cycle timing chart 5 (/lb, /ub independent controlled) t wc t as t wc t as a1 a2 a3 t wr t wr t dw t dh t dw t dh t bw t bw t aso /oe (input) t ohah t oes t oeh t bp /cs (input) address (input) data in d2 i/o0 to i/o7 (input) high-z high-z high-z high-z /we (input) data in d1 /lb (input) /ub (input) i/o8 to i/o15 (input) cautions 1. during address transition, at least one of pins /cs and /we, or both of /lb and /ub pins should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. in write cycle, mode and /oe should be fixed to high level. remark write operation is done during the overlap time of a low level /cs, /we, /lb and/or /ub.
preliminary data sheet m15867ej5v0ds 28 pd4664312-x figure 6-12. mode register setting timing chart /lb, /ub (input) /we (input) /cs (input) address (input) /oe (input) i/o (input) t rc t rc t wc t wc 3fffffh t wp t wr t wp t wr t dw t dh t dw t dh 3fffffh 3fffffh 3fffffh xxxxh xxxxh mode register setting high-z high-z high-z figure 6-13. mode register setting flow chart start end address= 3fffffh read with toggled the /cs, /oe address = 3fffffh write data = 00h? no mode register setting exit fail address = 3fffffh write data = xxh? no note note xxh = 04h, 05h, 06h, 07h no no no no address= 3fffffh read with toggled the /cs, /oe
preliminary data sheet m15867ej5v0ds 29 pd4664312-x figure 6-14. standby mode 2 (data hold: 16m bits / 8m bits / 4m bits) entry / exit timing chart /cs (input) t chml t mhcl1 mode (input) standby mode 1 standby mode 2 (data hold: 16m bits / 8m bits / 4m bits) figure 6-15. standby mode 2 (data not held) entry / exit timing chart /cs (input) t chml t mhcl2 mode (input) standby mode 1 standby mode 2 (data not held)
preliminary data sheet m15867ej5v0ds 30 pd4664312-x 7. package drawing a s b 10 9 8 7 6 5 4 3 2 1 cba d e f g h j k l m n p zd ze a a1 a2 index mark e ys y1 s item millimeters d e w e a a1 a2 b x y y1 zd ze 9.0 0.1 12.0 0.1 1.14 0.08 0.1 0.2 0.9 0.8 0.2 1.3 0.1 0.8 0.40 0.05 0.16 0.05 93-pin tape fbga (12x9) p93f9-80-cr2 s wb s wa s x bab m ? e d
preliminary data sheet m15867ej5v0ds 31 pd4664312-x 8. recommended soldering conditions please consult with our sales offices for soldering conditions of the pd4664312-x. type of surface mount device pd4664312f9-cr2: 93-pin tape fbga (12 x 9)
preliminary data sheet m15867ej5v0ds 32 pd4664312-x 9. revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 5th edition/ throughout throughout deletion class -c75x, -c85x, -e85x, -e10x, aug. 2002 -be85x, -ce80x, -ce90x modification supply voltage (chip) 2.6 to 3.1 v 2.7 to 3.1 v p.1 p.1 deletion features fast access time: 80, 85, 90, 100 ns fast page access time: 30, 35 ns pp.1, 15 pp.1, 15 modification operating supply current -be75x: tbd 40 ma p.17 pp.17, 18 addition read cycle t op (min.): 2ns p.20 p.22 modification figure 6-2 timing charts are modified. p.21 p.23 modification figure 6-3 timing charts are modified.
preliminary data sheet m15867ej5v0ds 33 pd4664312-x [ memo ]
preliminary data sheet m15867ej5v0ds 34 pd4664312-x [ memo ]
preliminary data sheet m15867ej5v0ds 35 pd4664312-x notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd4664312-x m8e 00. 4 the information in this document is current as of august, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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